1. Field of the Invention
The present invention is related to semiconductor devices and integrated circuits. More specifically, the present invention relates to Very Large Scale Integration (VLSI) systems.
2. Background Art
In VLSI applications the parasitic capacitance of the signal lines to the substrate reduces the signal bandwidth and signal speed due to the filtering effect. The parasitic capacitance arises from an electrical coupling between the signal line and the substrate. The equation for the parasitic capacitance is given by:C=eA/d,  Eq. 1where e is the dielectric constant of an insulator disposed between the signal lines and the substrate, d is the spacing between the signal lines and the substrate, and A is the area of the signal lines. The signal width times the signal length is the area of the signal lines. If, for example, the insulator is a field oxide, the dielectric constant, e, is about 3.9 and the thickness of the field oxide insulator, d, is about 0.3 μm.
The above equation suggests that the parasitic capacitance can be reduced by adjusting the parameters that appear on the right side of the equal symbol (e.g., e, A and d). For example, reducing the area, A, reduces the parasitic capacitance, but at the cost of proportionally increasing the parasitic resistance, which in turn decreases the signal speed. For a given VLSI process, adjusting the thickness, d, and the dielectric constant, e, is not a viable option. This is because for a fixed VLSI fabrication process, such as a standard complementary metal oxide semiconductor (CMOS) process, the thickness and dielectric constant of the insulator disposed between the signal lines and substrate remain constant. Accordingly, it is difficult to reduce the parasitic capacitance without changing the process material or flow.
Therefore, what is needed is a device and method that reduces the parasitic capacitance without changing the process material or flow.